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ADuC7060

Table 66. IRQVEC MMR Bit Designations

IRQP1 Register

Bit

31:23

Type

Read

Initial

Value

0

Description

Always read as 0.

Name:

Address:

IRQP1

0xFFFF0024

only

22:7

6:2

Read

only

Read

0

0

IRQBASE register value.

Highest priority IRQ source. This

Default value:

Access:

0x00000000

Read and write

only

is a value between 0 to 19 repre-

senting the possible interrupt

Table 68. IRQP1 MMR Bit Designations

sources. For example, if the highest

currently active IRQ is Timer1, then

these bits are [01000].

Bit

31

30:28

Name

Reserved

I2CMPI

Description

Reserved bit.

A priority level of 0 to 7 can be set for I 2 C

1:0

Reserved

0

Reserved bits.

master.

Priority Registers

The IRQ interrupt vector register, IRQVEC, points to a memory

address containing a pointer to the interrupt service routine of

the currently active IRQ. This register should be read only when

an IRQ occurs and IRQ interrupt nesting has been enabled by

setting Bit 0 of the IRQCONN register.

IRQP0 Register

27

26:24

23

22:20

19

18:16

15

Reserved

IRQ1PI

Reserved

IRQ0PI

Reserved

SPIMPI

Reserved

Reserved bit.

A priority level of 0 to 7 can be set for IRQ1.

Reserved bit.

A priority level of 0 to 7 can be set for IRQ0.

Reserved bit.

A priority level of 0 to 7 can be set for SPI

master.

Reserved bit.

Name:

Address:

Default value:

IRQP0

0xFFFF0020

0x00000000

14:12

11

10:8

7:0

UARTPI

Reserved

ADCPI

Reserved

A priority level of 0 to 7 can be set for UART.

Reserved bit.

A priority level of 0 to 7 can be set for the

ADC interrupt source.

Reserved bits.

Access:

Read and write

IRQP2 Register

Table 67. IRQP0 MMR Bit Designations

Name:

IRQP2

Bit

31:27

26:24

23

Name

Reserved

T3PI

Reserved

Description

Reserved bits.

A priority level of 0 to 7 can be set for

Timer3.

Reserved bit.

Address:

Default value:

Access:

0xFFFF0028

0x00000000

Read and write

22:20

19

18:16

T2PI

Reserved

T1PI

A priority level of 0 to 7 can be set for

Timer2.

Reserved bit.

A priority level of 0 to 7 can be set for

Timer1.

Table 69. IRQP2 MMR Bit Designations

Bit Name Description

31:15 Reserved Reserved bit.

14:12 IRQ3PI A priority level of 0 to 7 can be set for IRQ3.

15

14:12

11:7

6:4

3:0

Reserved

T0PI

Reserved

SWINTP

Reserved

Reserved bit.

A priority level of 0 to 7 can be set for

Timer0.

Reserved bits.

A priority level of 0 to 7 can be set for the

software interrupt source.

Interrupt 0 cannot be prioritized.

11

10:8

7

6:4

3

2:0

Reserved

IRQ2PI

Reserved

SPISPI

Reserved

I2CSPI

Reserved bit.

A priority level of 0 to 7 can be set for IRQ2.

Reserved bit.

A priority level of 0 to 7 can be set for SPI

slave.

Reserved bit.

A priority level of 0 to 7 can be set for I 2 C

slave.

Rev. 0 | Page 57 of 100

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